1. Field of the Invention
The present invention relates to data read circuits for reading data stored in memories of semiconductor integrated circuits, and more particularly, to a method of setting a reference voltage inputted to a sense amplifier.
2. Description of the Background Art
FIG. 5 is a schematic diagram showing the configuration of a general memory. An address bus 101 transmits the address data sent from an exterior (e.g., a CPU) to a memory 100. An address buffer 102 distributes the address data sent from the address bus 101, to a word decoder 104 and a bit decoder 105. A memory cell array 103 has a plurality of data memory cells (not shown) for storing data of "1" or "0", which are arranged in the form of a matrix. A word line 106 and a bit line 107 are connected to each data memory cell constituting the memory cell array 103. The word decoder 104 selects a desired word line designated by the address data, from a plurality of word lines 106. The bit decoder 105 selects a desired bit line designated by the address data, from a plurality of bit lines 107. A sense amplifier 108 detects and amplifies the data stored in a data memory cell that resides in the intersection of the word line 106 and the bit line 107 which have been selected by the word decoder 104 and the bit decoder 105, respectively. A data bus 109 transmits the data outputted from the sense amplifier 108 to the exterior of the memory 100 (e.g., a CPU).
FIG. 6 is a block diagram showing the configuration of a conventional data read circuit. That is, FIG. 6 shows a data read circuit per bit in the memory 100 of FIG. 5. A memory cell 110 corresponds to one of a plurality of data memory cells constituting the memory cell array 103 of FIG. 5. The memory cell 110 comprises a memory transistor 111 having a floating gate, and constitutes an EPROM (electrically programmable read only memory). A gate (G), a drain (D) and a source (S) of the memory transistor 111 are connected to a word line 106a, a bit line 107a and a ground, respectively. Here, the word line 106a and the bit line 107a correspond to one of a plurality of word lines 106 and bit lines 107 in FIG. 5, respectively. The bit line 107a is connected to a selector 105a. The selector 105a corresponds to part of the bit decoder 105 in FIG. 5, and connects a wire 113 and the bit line 107a. A pull-up circuit 112 applies a specified voltage to the bit line 107a through the wire 113 and the selector 105a. A sense amplifier 108a has two input terminals 114, 115. To the input terminal 114, the voltage of the wire 113 is inputted through a node ND.sub.1.
A reference voltage generating circuit 122 mainly comprises a memory transistor 116, a selector 119, and a pull-up circuit 121. Like the memory transistor 111, the memory transistor 116 comprises an EPROM cell having a floating gate. The source, drain, and gate of the memory transistor 116 are connected to a ground, a wire 118, and a wire 117, respectively. The wire 118 is connected to the selector 119, which is connected to a pull-up circuit 121 through a wire 120 having a node ND.sub.2. To the input terminal 115 of the sense amplifier 108a, the voltage of the wire 120 is inputted as a reference voltage V.sub.REF, through the node ND.sub.2.
Hereafter, the operation of reading data stored in a memory cell 110 will be described. Firstly, a word line 106a applies a voltage to the gate of a memory transistor 111. According to the storage content of the memory cell 110, the memory transistor 111 enters ON or OFF state, so that two types of, i.e., high and low, voltages V.sub.1, V.sub.2 are inputted to an input terminal 114 of a sense amplifier 108a .
To other input terminal 115 of the sense amplifier 108a, for example, an intermediate voltage of the voltages V.sub.1, V.sub.2 is inputted as a reference voltage V.sub.REF. At this time, the pull-up circuit 121, the selector 119 and the memory transistor 116 are properly selected so as to set a desired value of the reference voltage V.sub.REF.
The sense amplifier 108a compares a voltage V.sub.1 or V.sub.2 inputted to the input terminal 114 with a reference voltage V.sub.REF inputted to the input terminal 115, and amplifies its result and then outputs it.
In the conventional data read circuits so configured, however, in order to set a proper reference voltage V.sub.REF, a reference voltage generating circuit 122 must be organized by complicated selections. That is, a pull-up circuit 121 for applying a desired voltage, and a memory transistor 116 and a selector 119 that cause a desired voltage drop, are selected depending on the characteristics of a memory transistor 111 and a pull-up circuit 112, and on the load of a selector 105a.
Meanwhile, even if a reference voltage generating circuit 122 can be organized by a proper selection of elements, aged deterioration may change the characteristics of the elements to alter a reference voltage V.sub.REF. It is, however, impossible to reset a reference voltage V.sub.REF, resulting in a short product-life cycle.